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Ordering number : EN4868A
CMOS LSI
LC7872E
CD Graphics Decoder
Overview
The LC7872E is a CMOS LSI that integrates in a single chip the signal processing functions required for compact disk graphics (CD-G) decoding. The LC7872E accepts the subcode R to W signals output by a CD-DSP chip such as the Sanyo LC786X series, LC7862XE series or LC7863XE series and performs de-interleaving, error detection and correction, graphics instruction processing and image processing.
Features
* A CD-G decoder can be implemented with just two chips: a controller is not required. * Silicon gate CMOS structure for low power operation * Single 5 V power supply * 64-pin QFP (QIP) package
Package Dimensions
unit: mm 3159-QFP64E
[LC7872E]
Functions
* Built-in RGB encoder allows a CD-G decoder to be implemented in just two chips: the LC7872E and an external 64-kword x 4-bit DRAM * Interpolation and protection for the CD subcode synchronization signals as well as de-interleaving, error detection and correction for the R to W signals. * Two crystal oscillator systems, one for NTSC and one for PAL are provided and can be switched easily using the control pin provided. The standard clock and all required internal timings can be generated by connecting a 14.31818 MHz crystal for NTSC and/or a 17.734476 MHz crystal for PAL. * The LC7872E performs CD graphics instruction processing and drawing processing and controls the image display. * Composition video 8-bit D/A converter output provided * Superimposition support * Microprocessor interface provided to support set upgrades. * Define transparency support * Color bar output function
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
SANYO: QFP64E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
O3097HA (OT)/20695TH (OT) No. 4868-1/17
LC7872E Block Diagram
DB0 to DB3
A0 to A7
Microcontroller interface
TRANS0 to TRANS5
Pin Assignment
No. 4868-2/17
LC7872E
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Maximum input voltage Maximum output voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max VOUT max Pd max Topr Tstg Conditions Ratings VSS - 0.3 to +7.0 VSS - 0.3 to VDD + 0.3 VSS - 0.3 to VDD + 0.3 300 -30 to +85 -40 to +125 Unit V V V mW C C
Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Supply voltage Symbol VDD VIH (1) Input high level voltage VIH (2) VIH (3) VIL (1) Input low level voltage VIL (2) VIL (3) High level clock pulse width Low level clock pulse width Data setup time Data hold time CE wait time CE setup time CE hold time DO setup time toH toL tDS tDH tCP tCS tCH tDOS fin (1) fin (2) Input frequency fin (3) VDD1, VDD2 RESET SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to DB3, PALID, HRESET, VRESET, N/P1, N/P2, SON S1, S2, CB, TEST, TEST1, LINE, DEN RESET SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to DB3, PALID, HRESET, VRESET, N/P1, N/P2, SON S1, S2, CB, TEST, TEST1, LINE, DEN CL: Figure 1 CL: Figure 1 CL, DI: Figure 1 CL, DI: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 CE, CL: Figure 1 CL, DO: Figure 1 XIN1 XIN2 4FSC2 NTSC mode PAL mode NTSC mode PAL mode 0.3 400 Conditions min 4.5 0.7 VDD 2.2 0.8 VDD VSS VSS VSS 400 400 200 200 400 400 400 130 14.31818 17.734476 14.31818 17.734476 3.58 4.43 5 300 typ max 5.5 VDD VDD VDD 0.3 VDD 0.8 0.2 VDD Unit V V V V V V V ns ns ns ns ns ns ns ns MHz MHz MHz MHz MHz MHz Vp-p ns
fin (4) Input amplitude Reset pulse width VIN tWRES
FSCIN
XIN1, XIN2, 4FSC2, FSCIN: sine wave, capacitive coupling RESET
Electrical Characteristics at Ta = 25C, VSS = 0 V, VDD = 5 V
Parameter Current drain Symbol IDD (1) IDD (2) IIH (1) IIH (2) VIL (1) VIL (2) Output high level voltage VOH VDD1 VDD2 S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, LINE, HRESET, VRESET, N/P1, N/P2, RESET, SON: VIN = VDD CB, TEST, TEST1, DEN: VIN = VDD S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, LINE, HRESET, VRESET, N/P1, N/P2, RESET, SON: VIN = VSS PALID: VIN = VSS SBCK, WE, RAS, CAS, OE, A0 to A7, DB0 to DB3, CDGM, TRANS0 to TRANS5, VSYNC, YS, CSYNC, EFLG, FSX, FSC: IO = -0.5 mA 30 -5 -200 VDD - 1 -100 -30 VDD 100 Conditions min typ 24 12 max 40 20 5 200 Unit mA mA A A A A V
Input high level current
Input low level current
Continued on next page. No. 4868-3/17
LC7872E
Continued from preceding page.
Parameter Symbol VOL (1) VOL (2) Output off leakage current Built-in feedback resistance 8-bit D/A converter reference voltage 8-bit D/A converter output resistance 8-bit D/A converter output level Random read/write cycle time Page mode cycle time RAS access time CAS access time Output turn-off delay time RAS precharge time RAS pulse width RAS pulse width (page mode) RAS hold time CAS hold time CAS pulse width CAS precharge time CAS precharge time (page mode) Row address setup time Row address hold time Column address setup time Column address hold time Read command setup time Read command hold time (referenced to CAS) Read command hold time (referenced to RAS) Write command setup time Write command hold time Write command pulse width Write data setup time Write data hold time CAS setup time (CAS before RAS) CAS hold time (CAS before RAS) RAS precharge * CAS active time Video setup time SBCK output delay time IOFF RX VREF RDA VDAC tRC tPC tRAC tCAC tOFF tRP tRAS tRASP tRSH tCSH tCAS tCPN tCP tASR tRAH tASC tCAH tRCS tRCH tRRH tWCS tWCH tWP tDS tDH tCSR tCHR tRPC tVS tSD fSC tPWS Conditions SBCK, WE, RAS, CAS, OE, A0 to A7, DB0 to DB3, CDGM, TRANS0 to TRANS5, VSYNC, YS, CSYNC, EFLG, FSX, FSC: IO = 2 mA DO: IO = 5 mA DO, DB0 to DB3 XIN1, XIN2, 4FSC2, FSCIN VIDEO VIDEO VIDEO: Figure 9 Figures 2 and 3 Figures 4 and 5 Figure 2 Figures 2 and 4 Figures 2 and 4 Figures 2, 3, 4, 5 and 6 Figures 2, 3 and 6 Figures 4 and 5 Figures 2, 3, 4 and 5 Figures 2 and 3 Figures 2, 3, 4 and 5 Figure 6 Figures 4 and 5 Figures 2, 3, 4 and 5 Figures 2, 3, 4 and 5 Figures 2, 3, 4 and 5 Figures 2, 3, 4 and 5 Figure 2 Figure 2 Figure 2 Figure 3 Figure 3 Figure 3 Figure 3 Figure 3 Figure 6 Figure 6 Figure 6 Superimposition: Figure 7 NTSC mode: Figure 8 PAL mode: NTSC mode: Figure 8 PAL mode: Figure 8 100 60 120 60 50 50 100 50 0 50 150 120 120 100 50 150 100 100 50 50 50 20 4.74 4.79 224 222 25 5.03 5.08 100 120 18000 250 130 210 10 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s kHz kHz ns 2.40 min VSS VSS -5 1 2.45 300 2.50 typ max 0.4 0.75 +5 Unit V V A M V
Output low level voltage
SBCK cycle frequency PW setup time
No. 4868-4/17
LC7872E
Figure 1 Microcontroller Interface Timing
A0 to A7
DB0 to DB3
Figure 2 DRAM Read Cycle
No. 4868-5/17
LC7872E
A0 to A7
DB0 to DB3
Figure 3 DRAM Early Write Cycle
A0 to A7
DB0 to DB3
Figure 4 DRAM Page Mode Read Cycle
No. 4868-6/17
LC7872E
A0 to A7
DB0 to DB3
Figure 5 DRAM Page Mode Write Cycle
Figure 6 DRAM CAS before RAS Refresh Cycle
Figure 7 Phase Relationships in Superimposition Mode
No. 4868-7/17
LC7872E
Pin S1 = Pin S2 = High
Figure 8 Subcode Interface
Figure 9 Composite Video 8-Bit Digital Values (Color Bar Output) at VDD2 = 5 V
No. 4868-8/17
LC7872E Pin Functions
Pin No. 1 Symbol S1 I/O I CD DSP selection 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 S2 SBCK SFSY PW SBSY VDD1 CE DO DI CL MUTE VSS1 WE RAS A0 A1 A2 A3 A4 A5 A6 A7 DB0 CAS DB1 OE DB2 DB3 CB CDGM TRANS0 TRANS1 TRANS2 TRANS3 TRANS4 TRANS5 VSS2 VDD2 BIAS VIDEO TEST LINE FSCIN VSYNC TEST1 YS CSYNC 4FSC2 EFLG I O I I I -- I O I I I -- O O O O O O O O O O I/O O I/O O I/O I/O I O O O O O O O -- -- O O I I I O I O O I O Subcode R to W readout clock Subcode frame synchronization signal Subcode R to W data Subcode block synchronization signal Digital system power supply Serial input or control pin during serial output Serial data output (N-ch open drain) Serial data input Serial data I/O clock Control signal that invalidates the subcode data Digital system ground DRAM control DRAM control DRAM address DRAM address DRAM address DRAM address DRAM address DRAM address DRAM address DRAM address DRAM data DRAM control DRAM data DRAM control DRAM data DRAM data High: color bar output Low: normal mode (pull-down resistor built in) Function S1 0 1 1 S2 0 0 1 CD DSP LC7861N/67 LC7860K/63 LC7868/69/681
Outputs a high level when a CD-G disk detected Transparency digital output Transparency digital output Transparency digital output Transparency digital output Transparency digital output Transparency digital output Composite video D/A converter ground Composite video D/A converter power supply Ripple exclusion capacitor connection Composite video output (8-bit D/A converter output) Test pin. Must be tied low in normal operation (pull-down resistor built in) When pin NP2 is high: High: 263H, Low: 262H When pin NP2 is low: High: 312H, Low: 314H Subcarrier clock input (feedback resistor built in) Vertical synchronization signal output Test pin. Must be tied low in normal operation (pull-down resistor built in) Superimposition control output Composite synchronization signal output Superimposition mode external clock input (feedback resistor built in) Error state monitor
Continued on next page. No. 4868-9/17
LC7872E
Continued from preceding page.
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol FSX DEN PALID HRESET FSC VRESET RESET N/P1 N/P2 SON XIN2 XOUT2 XIN1 XOUT1 I/O O I I I O I I I I I I O I O Error state monitor trigger Disk information display enable pin High: BGC (pull-down resistor built in) Low: Enable Function
Superimposition PAL mode external control (pull-up resistor built in) Horizontal timing external control Subcarrier clock output Vertical timing external control Reset input NTSC/PAL selection NTSC/PAL selection Superimposition on/off Crystal oscillator connection 17.734476 MHz (PAL) Crystal oscillator connection 17.734476 MHz (PAL) Crystal oscillator connection 14.31818 MHz (NTSC) Crystal oscillator connection 14.31818 MHz (NTSC) High: NTSC (RGB encoder) Low: PAL High: NTSC (CD-G decoder) Low: PAL NTSC mode: 3.579545 MHz PAL mode: 4.433619 MHz
CD-G Instructions The LC7872E supports the following instructions that appear in the R to W subcodes as described in the CD Red Book. 1. MODE = 0, ITEM = 0 ZERO mode 2. MODE = 1, ITEM = 0 LINE GRAPHICS mode * Write FONT instruction (4) * Write Scroll SCREEN instruction (12) 3. MODE = 1, ITEM = 1 TV-GRAPHICS mode * Preset MEMORY instruction (1) * Preset BORDER instruction (2) * Write FONT FOREGROUND/BACKGROUND instruction (6) * Scroll SCREEN with preset instruction (20) * Scroll SCREEN with Copy instruction (24) * Load CLUT Color-0...7 instruction (30) * Load CLUT Color-8...15 instruction (31) * EXCLUSIVE-OR FONT instruction (38) * Define Color Transparency instruction (28)
No. 4868-10/17
LC7872E Pin Applications 1. Crystal Clock Oscillator; XIN1, XOUT1, XIN2, XOUT2, N/P1, N/P2, FSC, CSYNC, LINE and VSYNC The LC7872E provides two crystal oscillator systems as follows. Pins XIN1 and XOUT1 are for use with a 14.31818 MHz crystal oscillator (NTSC) Pins XIN2 and XOUT2 are for use with a 17.734476 MHz crystal oscillator (PAL) Crystals can be connected to either crystal system 1 or 2 according to the application, or both systems can be used under the control of pins N/P1 and N/P2 to implement an application that supports both video standards. The N/P1 pin switches the LC7872E RGB encoder block between NTSC and PAL and the N/P2 pin switches the decoder block between NTSC and PAL. The FSC pin outputs a clock that is the crystal oscillator frequency divided by four. The CSYNC pin is the composite synchronization signal output and VSYNC is the vertical synchronization signal output. The LINE pin switches the number of lines on a screen. The table below lists the pin states in each mode.
XIN1, XOUT1 14.31818 MHz XIN2, XOUT2 * 17.734476 MHz N/P1 High N/P2 High Television system NTSC/M FSC 3.579545 MHz LINE H L H L H L CSYNC 16.71511323 ms 16.65155767 ms 19.96788628 ms 20.09588555 ms 16.73350841 ms 16.6698829 ms
* 14.30244 MHz
Low
Low
PAL/GBIDH
4.433619 MHz
*
Low
High
PAL/M
3.575611 MHz
2. Subcode Interface; S1, S2, SBSY, SFSY, PW, SBCK and MUTE The LC7872E supports three interface modes under the control of pins S1 and S2. When the MUTE pin is set high, SBSY and PW input is disabled and SBCK output stops.
S1 S2 Mode Low Low LC7861N/67 interface High Low LC7860K/63 interface High High LC7868/69/681 interface
The SBCK delivery condition is that SFSY be confirmed to be low about 2.2 s after the SFSY falling edge in LC7860K/63 interface mode. In the other interface modes, the condition is that SFSY be confirmed to be high and SBSY be confirmed to be low about 2.2 s after the SFSY rising edge. * LC7860 interface (Pin names in parentheses are LC7860 pins.)
Note: 1. PWSY will be high during the S0 and S1 periods. 2. The SBSY pin must be held low.
No. 4868-11/17
LC7872E * LC7861N/67 interface (Pin names in parentheses are DSP pins.)
* LC7868/69/681 interface Identical to the LC7861N/67 interface except that the SBCK polarity is reversed (the shift occurs on the rising edge). 3. DRAM Interface; A0 to A7, DB0 to DB3, RAS, CAS, WE, OE The LC7872E uses an external 64-kword x 4-bit DRAM. 4. Display Format; DEN, N/P1, N/P2, CSYNC, VRESET, HRESET, YS, VIDEO, PALID and TRANS0 to TRANS5 * Data to which error detection and correction has been applied is encoded by the RGB encoder and the 8-bit D/A converter output is output from the VIDEO pin. This circuit handles both NTSC and PAL formats and either mode can be specified using the N/P pins. See item 1 for details on the pin states for the NTSC and PAL specifications. * The 4FSC2, FSCIN, YS, VRESET, HRESET, PALID and TRANS0 to TRANS5 pins are used in superimposition mode. The image may be disrupted if the VRESET and HRESET signals are not synchronized with 4FSC2. The PALID pin is controlled in PAL mode, and is used to match the LC7872E burst signal to the burst component of the external video signal. When this pin is high, the phase of the burst signal changes every horizontal period, and when this pin is low, the phase does not change. The YS pin outputs a control signal used to switch between an external video signal and the LC7872E video signal. The output conditions for this signal are set by the 2N byte command input registers 0, E, F, and G. The pins TRANS0 through TRANS5 output signals according to the define transparency instruction. * The DEN pin is a display control pin. The internal font data is output when DEN is low and the color data set up in the registers is used when DEN is high. The default state is blue.
No. 4868-12/17
LC7872E 5. CD Graphics Monitor; CDGM The CDGM pin goes high when the LC7872E receives any CD-G instruction. Since once this pin goes high it remains high as long as power is applied, using this pin requires a reset when the disk is changed. 6. Video Output; VIDEO A composite video signal is output from the VIDEO pin. The output level of the 8-bit D/A converter is 2.5 Vp-p. Therefore only an external 75 driver is required to acquire a 1 Vp-p rated output. 7. Error Flag Output; EFLG and FSX The result of the error detection process can be monitored from the EFLG pin.
8. Color Bar Output; CB The VIDEO pin outputs a color bar pattern when the CB pin is set high. The tables below describe this color bar pattern.
RGB Mixture Ratio (HEX)
Item WHITE GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BORDER (BLACK) R F B F 0 0 F F 0 0 G F B F F F 0 0 0 0 B F B 0 F 0 F 0 F 0
No. 4868-13/17
LC7872E Microcontroller Interface (CCB Bus) 1. 2N byte input command
Address (F4h): lsb [ 0 0 1 0 1 1 1 1 ] msb Control item: lsb [ 0 - - - A A A A ] msb; Where AAAA is the register number. Register 0 (mode setting) Data: lsb [ A B C D E F G H ] msb; Default: [ 0 0 0 0 0 1 1 0 ] A = VRAM/BG 0: Display the contents of VRAM 1: Display the background color (BGC) B = TV/LINE 0: TV graphics mode 1: Line graphics mode C = Disk command enable 0: Only disk commands are accepted. 1: Disk commands are ignored and only MGC is accepted. D = Color bar on/off 0: Off 1: Color bar on EFG = Comparison conditions in superimposition mode (only valid when SON = 1) EF = 00: Comparison not performed. 01: When the border color is not black, YS is set high (display) for section whose color does not match the border color and is set low (clear) otherwise. 11: YS is set high for sections that do not match the chroma key color, and is set low otherwise. G = 0: The whole screen is set low (clear) when the comparison condition does not hold for EF = 00 and EF = 01. G = 1: The whole screen is set high (display) when the comparison condition does not hold for EF = 00 and EF = 01. H = INIT 0: Normal 1: Internal reset On an internal reset the display screen is set to a blue background screen. Register 1 (screen position adjustment) Data: lsb [ H H H H V V V V ] msb; Default: [ 0 0 0 0 0 0 0 0 ] H = horizontal direction. The value is specified as a two's complement value with left being the positive direction. Position is adjustable in two dot units from -16 to +14 dots from the center. V = vertical direction. The value is specified as a two's complement value with up being the positive direction. Position is adjustable in two dot units from -16 to +14 dots from the center. Register 2 (on/off settings for channels 0 to 7) Data: lsb [ C C C C C C C C ] msb; Default: [ 1 1 0 0 0 0 0 0 ] C = channel 0 to 7 0: off 1: on
No. 4868-14/17
LC7872E Register 3 (on/off settings for channels 8 to 15) Data: lsb [ C C C C C C C C ] msb; Default: [ 0 0 0 0 0 0 0 0 ] C = channel 8 to 15 0: off 1: on Register 4 (BGC R and G setting) Data: lsb [ R R R R G G G G ] msb; Default: [ 0 0 0 0 0 0 0 0 ] Register 5 (BGC B setting) Data: lsb [ B B B B - - - - ] msb; Default: [ 0 1 0 1 - - - - ] Register 6 (chroma key color R and G settings) Data: lsb [ R R R R G G G G ] msb; Default: [ 0 0 0 0 0 0 0 0 ] Register 7 (chroma key color B setting) Data: lsb [ B B B B - - - - ] msb; Default: [ 0 0 0 0 - - - - ] Register 8 (burst phase setting, only valid when SON = 1) Data: lsb [ F F - - - - - P ] msb; Default: [ 0 0 - - - - - 0 ] Register 9 (YS and TRANS output timing) Data: lsb [ T T T - - - - - ] msb; Default: [ 0 0 1 - - - - - ] T = phase setting. The phase difference between YS and TRANS (the digital output) and the video signal can be set to one of 8 levels from 0 to 7 in units of single 4FSC clock cycles. At a value of 4 the phase is identical to that of the VIDEO pin. Register 10 (External synchronization on/off, test mode) Data: lsb [ T T T - - Y S R ] msb; Default: [ 0 0 0 - - - 0 0 ] T = test mode setting R = 0:Only the display area is moved 1:Motion also includes the border area (only left/right motion supported) S = 0:Normal 1:Initializes the TLUT contents to all 0.* Y = 0:Resets HRESET and VRESET when an external clock is used (SON = 1) 1:Resets VRESET when an external clock is used (SON = 1) (HRESET is not required) Note: * In this state the define transparency command will not be accepted. (Return the system to the S = 0 state.) Register 11 (subtitle scrolling, vertical) Data: lsb [ V V V V V - - - ] msb; Default: [ 0 0 0 0 0 - - - ] This setting allows the subtitle screen display position to be scrolled in font height units. V = vertical (up) scrolling distance (0 to 17 font height units) Register 12 (subtitle scrolling, horizontal) Data: lsb [ H H H H H H - - ] msb; Default: [ 0 0 0 0 0 0 - - ] This setting allows the subtitle screen display position to be scrolled in font width units. H = horizontal (left) scrolling distance (0 to 49 font width units) Register 13 (TRANS setting, only valid when SON = 1) Data: lsb [ B B B B B B - P ] msb; Default: [ 0 0 0 0 0 0 - 1 ] P = 1: Enables the TRANS setting. 0: Invalid (The whole screen is displayed and burst goes to the CDG side.) B = the BGC TRANS value
No. 4868-15/17
LC7872E 2. 19-byte input command (MGC write)
Address (F4h): lsb [ 0 0 1 0 1 1 1 1 ] msb Control item: lsb [ 1 - - - - - - - ] msb Data: lsb [ - - WV U T S R ] msb; R to W is the subcode input. This command is executed on the CE falling edge. 3. 19-byte output command (packed data readout)
Address (F5h): lsb [ 1 0 1 0 1 1 1 1 ] msb Check flags: lsb [ A B C D Q Q P P ] msb Data: lsb [ - - WV U T S R ] msb A = Set to 1 when the following 18 bytes are guaranteed and furthermore this is the first data item read out. (The readout operation must be completed within 1.1 ms.) B = 0: Command execution in progress 1: Command wait state C = VBLANK:Set to 1 during the vertical blanking period D = Disk identifier flag 0: CD 1: CD-G Q = QF0 and QF1 (Q error correction flags) P = PF0 and PF1 (P error correction flags) Note that when it is not necessary to read out all 19 bytes, the readout can be interrupted at any point in byte units. (In particular, this command can be used to read out only the check flags.)
No. 4868-16/17
LC7872E NTSC Application Circuit Using the LC7872E
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of October, 1997. Specifications and information herein are subject to change without notice. No. 4868-17/17

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